
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (2,5) (M/ S = V IH ) (4)
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
t APS
DATA IN "A"
(1)
t DW
VALID
t DH
ADDR "B"
MATCH
BUSY "B"
t WDD
DATA OUT "B"
t DDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/S = V IL (SLAVE).
2. CE L = CE R = V IL
3. OE = V IL for the reading port.
4. If M/ S = V IL (slave) then BUSY is input ( BUSY "A" = V IH ) and BUSY "B" = "don't care", for this example.
5. All timing is the same for left and right port. Port "A' may be either left or right port. Port "B" is the port opposite from Port "A".
Timing Waveform of Write with BUSY
t WP
R/ W "A"
t WB (3)
t BDA
t BDD
VALID
2739 drw 13
BUSY "B"
R/ W "B"
(2)
t WH (1)
2739 drw 14
NOTES:
1. t WH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B", blocking R/ W "B" , until BUSY "B" goes HIGH.
3. t WB is only for the 'Slave' Version .
13
6.42